Fin type field effect transistors (FinFETs) are well known in the micro-circuitry arts; see for example co-owned U.S. Pat. Nos. 6,921,982; 8,362,568; 8,617,426; 8,799,848 and 8,722,494. FinFETs are typically complementary metal-oxide semiconductor (CMOS) devices in which the channel of the transistor is characterized in having a substantial dimension perpendicular to the base on which the channel lies. Among other advantages this physical layout allows the transistor's gate to cover the top and both sides of the channel, enabling more effective gate control and better reducing current leakage.
FinFETs are widely deployed in arrays in which parallel fins 10 are controlled by a common gate 11 or finger as shown at FIG. 1A. Typically there is a dielectric spacer 12 about the gate 11, commonly formed of an oxide, nitride, and/or oxynitride such as a silicon oxide or a silicon nitride (or carbon and/or boron doped oxides or oxynitirides of silicon) which during manufacture of the host chip is deposited via chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) or physical vapor deposition (PVD) and etched using reactive ion etching (RIE) for example. On the chip substrate there may be an epitaxially grown source-drain region adjacent to the ends of the fins 10 which is shown in FIG. 1B as the epi-merge region 14 and operates to merge the sources and drains of multiple fins. Further details of such an epitaxially grown source-drain region can be seen at co-owned US Patent Application Publication No. 2014/0167163, the contents of which are hereby incorporated by reference. In the epi-merge region 14 in a FinFET array a cladding layer 15 is typically grown epitaxially on the fin 10 to insert dopants that form the junction for current injection into the channel.
Current leakages and parasitic capacitances that are negligible in larger electronic devices become first order limits as transistors scale to line widths of 40 nm and less. FIG. 1C is an expanded view of the inset from FIG. 1B, and shows the spacer layer has an overlay capacitance Cov and also the epi-merge source/drain region 14 has a source/drain (S/D) capacitance Ceff. It is preferable to be able to set the overlay capacitance Cov relatively high to ensure good isolation of the gate from the source and drain and it is also preferable to have the S/D capacitance Ceff of the epi-merge source/drain regions 14 optimized for faster switching. Relevant teachings in this regard may be seen in a paper by V. Subramanian et al. entitled Identifying bottlenecks to the RF performance of FinFETs [23RD INTERNATIONAL CONFERENCE ON VLSI DESIGN, 2010; pages 111-116]. But in the current state of the art Cov and Ceff are set by the same geometry; the thickness of the spacer layer and the dielectric constant K of the material from which it is made can be designed to yield a high overlay capacitance Cov but this would also increase the S/D capacitance Ceff of the epi-merged source and drain regions 14. This same geometry also sets the diffusion of dopants from the cladding 15 into the extension of the fin 10 beyond the source and drain, and this diffusion is biased by the overlay capacitance Cov as FIG. 1C shows.
Embodiments of these teachings enable a high dopant dose and high overlay capacitance Cov with an optimized/D capacitance Ceff of the epi-merge source and drain regions 14.